//========== JD9365 B0E10.1 initial setting ==========//
//----------- JD EVB RGB setting -----------------//
JDEVB_RSOX(800);    
JDEVB_RSOY(1280);    
JDEVB_VS(4);
JDEVB_VBP(20);//8
JDEVB_VFP(20);//8    
JDEVB_HS(20);//4
JDEVB_HBP(20);//40
JDEVB_HFP(40); //40 
JDEVB_DSILANE(4);//DSI Lane
//JDEVB_PCLK(5);   //Index=8, 44.4MHZ   
JDEVB_DOTCLK(70.22);    
JDEVB_VCI(3.3);      //Dr.IC_VCI Power  
JDEVB_IOVCC(1.8);    //Dr.IC_IOVCC Power    
JDEVB_SSDIO(1.8);    //SSD_IOVCC Power
Delayms(10);

//-------------------------------------------------------------//




//JD9365 initial code

//Page0
SSD_Single(0xE0,0x00);
//--- PASSWORD  ----//
SSD_Single(0xE1,0x93);
SSD_Single(0xE2,0x65);
SSD_Single(0xE3,0xF8);
SSD_Single(0x80,0x03);


//--- Page1  ----//
SSD_Single(0xE0,0x01);
//Set VCOM
SSD_Single(0x00,0x00);
SSD_Single(0x01,0x3B);
//Set VCOM_Reverse
//SSD_Single(0x03,0x00);
//SSD_Single(0x04,0xA0);

SSD_Single(0x0C,0x74);

//Set Gamma Power, VGMP,VGMN,VGSP,VGSN
SSD_Single(0x17,0x00);
SSD_Single(0x18,0xAF);//VGMP=4.8V
SSD_Single(0x19,0x00);//VGSP=0.3V
SSD_Single(0x1A,0x00);
SSD_Single(0x1B,0xAF);
SSD_Single(0x1C,0x00);


//SETPANEL
SSD_Single(0x35,0x26);	//ASP=0110

//SETPANEL
SSD_Single(0x37,0x09);	//SS=1,BGR=1

//SET RGBCYC
SSD_Single(0x38,0x04);	//JDT=100 column inversion
SSD_Single(0x39,0x00);	//RGB_N_EQ1, 0x12
SSD_Single(0x3A,0x01);	//RGB_N_EQ2, 0x18
SSD_Single(0x3C,0x78);	//SET EQ3 for TE_H
SSD_Single(0x3D,0xFF);	//SET CHGEN_ON, 
SSD_Single(0x3E,0xFF);	//SET CHGEN_OFF, 
SSD_Single(0x3F,0x7F);	//SET CHGEN_OFF2,

//Set TCON
SSD_Single(0x40,0x06);	//RSO=800 RGB
SSD_Single(0x41,0xA0);	//LN=640->1280 line
SSD_Single(0x42,0x81);	//SLT
SSD_Single(0x43,0x14);	//VFP=20
SSD_Single(0x44,0x23);	//VBP=24
SSD_Single(0x45,0x28);  //HBP=40

//--- power voltage  ----//
SSD_Single(0x55,0x02);	//DCDCM=0001, JD PWR_IC
SSD_Single(0x57,0x69);
SSD_Single(0x59,0x0A);	//VCL = -2.9V
SSD_Single(0x5A,0x2A);	//VGH = 15V
SSD_Single(0x5B,0x17);	//VGL = -11V

//--- Gamma  ----//
SSD_Single(0x5D,0x7F);
SSD_Single(0x5E,0x6B);
SSD_Single(0x5F,0x5C);
SSD_Single(0x60,0x4F);
SSD_Single(0x61,0x4D);
SSD_Single(0x62,0x3F);
SSD_Single(0x63,0x42);
SSD_Single(0x64,0x2B);
SSD_Single(0x65,0x44);
SSD_Single(0x66,0x43);
SSD_Single(0x67,0x43);
SSD_Single(0x68,0x63);
SSD_Single(0x69,0x52);
SSD_Single(0x6A,0x5A);
SSD_Single(0x6B,0x4F);
SSD_Single(0x6C,0x4E);
SSD_Single(0x6D,0x20);
SSD_Single(0x6E,0x0F);
SSD_Single(0x6F,0x00);

SSD_Single(0x70,0x7F);
SSD_Single(0x71,0x6B);
SSD_Single(0x72,0x5C);
SSD_Single(0x73,0x4F);
SSD_Single(0x74,0x4D);
SSD_Single(0x75,0x3F);
SSD_Single(0x76,0x42);
SSD_Single(0x77,0x2B);
SSD_Single(0x78,0x44);
SSD_Single(0x79,0x43);
SSD_Single(0x7A,0x43);
SSD_Single(0x7B,0x63);
SSD_Single(0x7C,0x52);
SSD_Single(0x7D,0x5A);
SSD_Single(0x7E,0x4F);
SSD_Single(0x7F,0x4E);
SSD_Single(0x80,0x20);
SSD_Single(0x81,0x0F);
SSD_Single(0x82,0x00);


                                 
//Page2, for GIP                                      
SSD_Single(0xE0,0x02);                                
//GIP_L Pin mapping    
SSD_Single(0x00,0x02);  //STV3	->	STV2
SSD_Single(0x01,0x02);	//Stv3	->	STV2
SSD_Single(0x02,0x00);	//STV4	->	STV0
SSD_Single(0x03,0x00);	//STV4	->	STV0
SSD_Single(0x04,0x1E);	//VDS	->	VGH
SSD_Single(0x05,0x1E);	//VDS	->	VGH
SSD_Single(0x06,0x1F);	//VSD	->	VGL
SSD_Single(0x07,0x1F);	//VSD	->	VGL
SSD_Single(0x08,0x1F);
SSD_Single(0x09,0x17);	//VDD2	->	FLM
SSD_Single(0x0A,0x17);	//VDD2	->	FLM
SSD_Single(0x0B,0x37);	//VDD1	->	INV_FLM
SSD_Single(0x0C,0x37);	//VDD1	->	INV_FLM
SSD_Single(0x0D,0x47);	//CLK8	->	CLK3
SSD_Single(0x0E,0x47);	//CLK8	->	CLK3
SSD_Single(0x0F,0x45);	//CLK6	->	CLK1
SSD_Single(0x10,0x45);	//CLK6	->	CLK1
SSD_Single(0x11,0x4B);	//CLK4	->	CLK7
SSD_Single(0x12,0x4B);	//CLK4	->	CLK7
SSD_Single(0x13,0x49);	//CLK2	->	CLK5
SSD_Single(0x14,0x49);	//CLK2	->	CLK5
SSD_Single(0x15,0x1F);	//VGL

//GIP_R Pin mapping 
SSD_Single(0x16,0x01);	//STV1	->	STV1
SSD_Single(0x17,0x01);	//STV1	->	STV1
SSD_Single(0x18,0x00);	//STV2	->	STV0
SSD_Single(0x19,0x00);	//STV2	->	STV0
SSD_Single(0x1A,0x1E);	//VDS	->	VGH
SSD_Single(0x1B,0x1E);	//VDS	->	VGH
SSD_Single(0x1C,0x1F);	//VSD	->	VGL
SSD_Single(0x1D,0x1F); 	//VSD	->	VGL
SSD_Single(0x1E,0x1F);
SSD_Single(0x1F,0x17);	//VDD2	->	FLM
SSD_Single(0x20,0x17);	//VDD2	->	FLM
SSD_Single(0x21,0x37);	//VDD1	->	INV_FLM
SSD_Single(0x22,0x37);	//VDD1	->	INV_FLM
SSD_Single(0x23,0x46);	//CLK7	->	CLK2
SSD_Single(0x24,0x46);	//CLK7	->	CLK2
SSD_Single(0x25,0x44);	//CLK5	->	CLK0
SSD_Single(0x26,0x44);	//CLK5	->	CLK0
SSD_Single(0x27,0x4A);	//CLK3	->	CLK6
SSD_Single(0x28,0x4A);	//CLK3	->	CLK6
SSD_Single(0x29,0x48);	//CLK1	->	CLK4
SSD_Single(0x2A,0x48);	//CLK1	->	CLK4
SSD_Single(0x2B,0x1F);	//VGL       
   
//GIP_L_GS Pin mapping
SSD_Single(0x2C,0x01);	//STV3	->	STV1
SSD_Single(0x2D,0x01);
SSD_Single(0x2E,0x00);	//STV4	->	STV0
SSD_Single(0x2F,0x00);
SSD_Single(0x30,0x1F);	//VDS	->	VGL
SSD_Single(0x31,0x1F);
SSD_Single(0x32,0x1E);	//VSD	->	VGH
SSD_Single(0x33,0x1E);
SSD_Single(0x34,0x1F);	//	
SSD_Single(0x35,0x17);	//VDD2	->	FLM
SSD_Single(0x36,0x17);
SSD_Single(0x37,0x37);	//VDD1	->	INV_FLM
SSD_Single(0x38,0x37);
SSD_Single(0x39,0x08);	//CLK8	->	CLK4
SSD_Single(0x3A,0x08);
SSD_Single(0x3B,0x0A);	//CLK6	->	CLK6
SSD_Single(0x3C,0x0A);
SSD_Single(0x3D,0x04);	//CLK4	->	CLK0
SSD_Single(0x3E,0x04);
SSD_Single(0x3F,0x06);	//CLK2	->	CLK2
SSD_Single(0x40,0x06);
SSD_Single(0x41,0x1F);	//VGL

//GIP_R_GS Pin mapping
SSD_Single(0x42,0x02);	//STV1	->	STV2	
SSD_Single(0x43,0x02);
SSD_Single(0x44,0x00);	//STV2	->	STV0	
SSD_Single(0x45,0x00);
SSD_Single(0x46,0x1F);	//VDS	->	VGL
SSD_Single(0x47,0x1F);
SSD_Single(0x48,0x1E);	//VSD	->	VGH
SSD_Single(0x49,0x1E);
SSD_Single(0x4A,0x1F);	//
SSD_Single(0x4B,0x17);	//VDD2	->	FLM
SSD_Single(0x4C,0x17);
SSD_Single(0x4D,0x37);	//VDD1	->	INV_FLM
SSD_Single(0x4E,0x37);
SSD_Single(0x4F,0x09);	//CLK7	->	CLK5	
SSD_Single(0x50,0x09);
SSD_Single(0x51,0x0B);	//CLK5	->	CLK7		
SSD_Single(0x52,0x0B);
SSD_Single(0x53,0x05);	//CLK3	->	CLK1		
SSD_Single(0x54,0x05);
SSD_Single(0x55,0x07);	//CLK1	->	CLK3	
SSD_Single(0x56,0x07);
SSD_Single(0x57,0x1F);	//VGL       

//GIP Timing  
SSD_Single(0x58,0x40); 
SSD_Single(0x5B,0x30); //STV_NUM,STV_S0
SSD_Single(0x5C,0x16); //STV_S0
SSD_Single(0x5D,0x34); //STV_W / S1
SSD_Single(0x5E,0x05); //STV_S2
SSD_Single(0x5F,0x02); //STV_S3
SSD_Single(0x63,0x00); //SETV_ON  
SSD_Single(0x64,0x6A); //SETV_OFF 
SSD_Single(0x67,0x73); 
SSD_Single(0x68,0x1D);//CKV_S0 
SSD_Single(0x69,0x08); 
SSD_Single(0x6A,0x6A); 
SSD_Single(0x6B,0x08); //Dummy clk

SSD_Single(0x6C,0x00); 
SSD_Single(0x6D,0x00); 
SSD_Single(0x6E,0x00); 
SSD_Single(0x6F,0x88); 

SSD_Single(0x75,0xFF);
SSD_Single(0x77,0xDD);//VEN_EN=1 
SSD_Single(0x78,0x3F);
SSD_Single(0x79,0x15); //0x0C 
SSD_Single(0x7A,0x17);//VEN_S0
SSD_Single(0x7D,0x14);//VEN_ON
SSD_Single(0x7E,0x82); //VEN_OFF


//Page4
SSD_Single(0xE0,0x04);
SSD_Single(0x00,0x0E);
SSD_Single(0x02,0xB3);
SSD_Single(0x09,0x61);
SSD_Single(0x0E,0x48);

//Page0
SSD_Single(0xE0,0x00);

SSD_Single(0xE6,0x02);
SSD_Single(0xE7,0x0C);


//SLP OUT

SSD_CMD(0x11);  	// SLPOUT
Delayms(120);

//DISP ON

SSD_CMD(0x29);  	// DSPON
Delayms(5);

//--- TE----//
SSD_Single(0x35,0x00);