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1
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//========== JD9365 B0E10.1 initial setting ==========//
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2
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//----------- JD EVB RGB setting -----------------//
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3
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JDEVB_RSOX(800);
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4
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JDEVB_RSOY(1280);
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5
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JDEVB_VS(4);
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6
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JDEVB_VBP(20);//8
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7
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JDEVB_VFP(20);//8
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8
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JDEVB_HS(20);//4
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9
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JDEVB_HBP(20);//40
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10
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JDEVB_HFP(40); //40
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11
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JDEVB_DSILANE(4);//DSI Lane
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12
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//JDEVB_PCLK(5); //Index=8, 44.4MHZ
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13
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JDEVB_DOTCLK(70.22);
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14
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JDEVB_VCI(3.3); //Dr.IC_VCI Power
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15
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JDEVB_IOVCC(1.8); //Dr.IC_IOVCC Power
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16
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JDEVB_SSDIO(1.8); //SSD_IOVCC Power
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17
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Delayms(10);
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18
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19
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//-------------------------------------------------------------//
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20
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21
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22
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23
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24
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//JD9365 initial code
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25
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26
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//Page0
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27
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SSD_Single(0xE0,0x00);
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28
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//--- PASSWORD ----//
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29
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SSD_Single(0xE1,0x93);
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30
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SSD_Single(0xE2,0x65);
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31
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SSD_Single(0xE3,0xF8);
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32
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SSD_Single(0x80,0x03);
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33
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34
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35
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//--- Page1 ----//
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36
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SSD_Single(0xE0,0x01);
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37
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//Set VCOM
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38
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SSD_Single(0x00,0x00);
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39
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SSD_Single(0x01,0x3B);
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40
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//Set VCOM_Reverse
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41
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//SSD_Single(0x03,0x00);
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42
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//SSD_Single(0x04,0xA0);
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43
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44
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SSD_Single(0x0C,0x74);
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45
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46
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//Set Gamma Power, VGMP,VGMN,VGSP,VGSN
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47
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SSD_Single(0x17,0x00);
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48
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SSD_Single(0x18,0xAF);//VGMP=4.8V
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49
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SSD_Single(0x19,0x00);//VGSP=0.3V
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50
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SSD_Single(0x1A,0x00);
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51
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SSD_Single(0x1B,0xAF);
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52
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SSD_Single(0x1C,0x00);
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53
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54
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55
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//SETPANEL
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56
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SSD_Single(0x35,0x26); //ASP=0110
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57
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58
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//SETPANEL
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59
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SSD_Single(0x37,0x09); //SS=1,BGR=1
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60
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61
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//SET RGBCYC
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62
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SSD_Single(0x38,0x04); //JDT=100 column inversion
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63
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SSD_Single(0x39,0x00); //RGB_N_EQ1, 0x12
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64
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SSD_Single(0x3A,0x01); //RGB_N_EQ2, 0x18
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65
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SSD_Single(0x3C,0x78); //SET EQ3 for TE_H
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66
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SSD_Single(0x3D,0xFF); //SET CHGEN_ON,
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67
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SSD_Single(0x3E,0xFF); //SET CHGEN_OFF,
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68
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SSD_Single(0x3F,0x7F); //SET CHGEN_OFF2,
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69
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70
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//Set TCON
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71
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SSD_Single(0x40,0x06); //RSO=800 RGB
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72
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SSD_Single(0x41,0xA0); //LN=640->1280 line
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73
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SSD_Single(0x42,0x81); //SLT
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74
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SSD_Single(0x43,0x14); //VFP=20
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75
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SSD_Single(0x44,0x23); //VBP=24
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76
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SSD_Single(0x45,0x28); //HBP=40
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77
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78
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//--- power voltage ----//
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79
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SSD_Single(0x55,0x02); //DCDCM=0001, JD PWR_IC
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80
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SSD_Single(0x57,0x69);
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81
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SSD_Single(0x59,0x0A); //VCL = -2.9V
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82
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SSD_Single(0x5A,0x2A); //VGH = 15V
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83
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SSD_Single(0x5B,0x17); //VGL = -11V
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84
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85
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//--- Gamma ----//
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86
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SSD_Single(0x5D,0x7F);
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87
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SSD_Single(0x5E,0x6B);
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88
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SSD_Single(0x5F,0x5C);
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89
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SSD_Single(0x60,0x4F);
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90
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SSD_Single(0x61,0x4D);
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91
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SSD_Single(0x62,0x3F);
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92
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SSD_Single(0x63,0x42);
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93
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SSD_Single(0x64,0x2B);
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94
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SSD_Single(0x65,0x44);
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95
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SSD_Single(0x66,0x43);
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96
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SSD_Single(0x67,0x43);
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97
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SSD_Single(0x68,0x63);
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98
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SSD_Single(0x69,0x52);
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99
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SSD_Single(0x6A,0x5A);
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100
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SSD_Single(0x6B,0x4F);
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101
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SSD_Single(0x6C,0x4E);
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102
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SSD_Single(0x6D,0x20);
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103
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SSD_Single(0x6E,0x0F);
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104
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SSD_Single(0x6F,0x00);
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105
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106
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SSD_Single(0x70,0x7F);
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107
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SSD_Single(0x71,0x6B);
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108
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SSD_Single(0x72,0x5C);
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109
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SSD_Single(0x73,0x4F);
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110
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SSD_Single(0x74,0x4D);
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111
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SSD_Single(0x75,0x3F);
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112
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SSD_Single(0x76,0x42);
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113
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SSD_Single(0x77,0x2B);
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114
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SSD_Single(0x78,0x44);
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115
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SSD_Single(0x79,0x43);
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116
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SSD_Single(0x7A,0x43);
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117
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SSD_Single(0x7B,0x63);
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118
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SSD_Single(0x7C,0x52);
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119
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SSD_Single(0x7D,0x5A);
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120
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SSD_Single(0x7E,0x4F);
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121
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SSD_Single(0x7F,0x4E);
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122
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SSD_Single(0x80,0x20);
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123
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SSD_Single(0x81,0x0F);
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124
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SSD_Single(0x82,0x00);
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125
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126
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127
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128
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//Page2, for GIP
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129
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SSD_Single(0xE0,0x02);
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130
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//GIP_L Pin mapping
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131
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SSD_Single(0x00,0x02); //STV3 -> STV2
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132
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SSD_Single(0x01,0x02); //Stv3 -> STV2
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133
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SSD_Single(0x02,0x00); //STV4 -> STV0
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134
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SSD_Single(0x03,0x00); //STV4 -> STV0
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135
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SSD_Single(0x04,0x1E); //VDS -> VGH
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136
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SSD_Single(0x05,0x1E); //VDS -> VGH
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137
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SSD_Single(0x06,0x1F); //VSD -> VGL
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138
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SSD_Single(0x07,0x1F); //VSD -> VGL
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139
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SSD_Single(0x08,0x1F);
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140
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SSD_Single(0x09,0x17); //VDD2 -> FLM
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141
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SSD_Single(0x0A,0x17); //VDD2 -> FLM
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142
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SSD_Single(0x0B,0x37); //VDD1 -> INV_FLM
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143
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SSD_Single(0x0C,0x37); //VDD1 -> INV_FLM
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144
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SSD_Single(0x0D,0x47); //CLK8 -> CLK3
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145
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SSD_Single(0x0E,0x47); //CLK8 -> CLK3
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146
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SSD_Single(0x0F,0x45); //CLK6 -> CLK1
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147
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SSD_Single(0x10,0x45); //CLK6 -> CLK1
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148
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SSD_Single(0x11,0x4B); //CLK4 -> CLK7
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149
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SSD_Single(0x12,0x4B); //CLK4 -> CLK7
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150
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SSD_Single(0x13,0x49); //CLK2 -> CLK5
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151
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SSD_Single(0x14,0x49); //CLK2 -> CLK5
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152
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SSD_Single(0x15,0x1F); //VGL
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153
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154
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//GIP_R Pin mapping
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155
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SSD_Single(0x16,0x01); //STV1 -> STV1
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156
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SSD_Single(0x17,0x01); //STV1 -> STV1
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157
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SSD_Single(0x18,0x00); //STV2 -> STV0
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158
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SSD_Single(0x19,0x00); //STV2 -> STV0
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159
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SSD_Single(0x1A,0x1E); //VDS -> VGH
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160
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SSD_Single(0x1B,0x1E); //VDS -> VGH
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161
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SSD_Single(0x1C,0x1F); //VSD -> VGL
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162
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SSD_Single(0x1D,0x1F); //VSD -> VGL
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163
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SSD_Single(0x1E,0x1F);
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164
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SSD_Single(0x1F,0x17); //VDD2 -> FLM
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165
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SSD_Single(0x20,0x17); //VDD2 -> FLM
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166
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SSD_Single(0x21,0x37); //VDD1 -> INV_FLM
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167
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SSD_Single(0x22,0x37); //VDD1 -> INV_FLM
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168
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SSD_Single(0x23,0x46); //CLK7 -> CLK2
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169
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SSD_Single(0x24,0x46); //CLK7 -> CLK2
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170
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SSD_Single(0x25,0x44); //CLK5 -> CLK0
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171
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SSD_Single(0x26,0x44); //CLK5 -> CLK0
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172
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SSD_Single(0x27,0x4A); //CLK3 -> CLK6
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173
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SSD_Single(0x28,0x4A); //CLK3 -> CLK6
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174
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SSD_Single(0x29,0x48); //CLK1 -> CLK4
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175
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SSD_Single(0x2A,0x48); //CLK1 -> CLK4
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176
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SSD_Single(0x2B,0x1F); //VGL
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177
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178
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//GIP_L_GS Pin mapping
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179
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SSD_Single(0x2C,0x01); //STV3 -> STV1
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180
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SSD_Single(0x2D,0x01);
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181
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SSD_Single(0x2E,0x00); //STV4 -> STV0
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182
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SSD_Single(0x2F,0x00);
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183
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SSD_Single(0x30,0x1F); //VDS -> VGL
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184
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SSD_Single(0x31,0x1F);
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185
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SSD_Single(0x32,0x1E); //VSD -> VGH
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186
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SSD_Single(0x33,0x1E);
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187
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SSD_Single(0x34,0x1F); //
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188
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SSD_Single(0x35,0x17); //VDD2 -> FLM
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189
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SSD_Single(0x36,0x17);
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190
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SSD_Single(0x37,0x37); //VDD1 -> INV_FLM
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191
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SSD_Single(0x38,0x37);
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192
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SSD_Single(0x39,0x08); //CLK8 -> CLK4
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193
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SSD_Single(0x3A,0x08);
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194
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SSD_Single(0x3B,0x0A); //CLK6 -> CLK6
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195
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SSD_Single(0x3C,0x0A);
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196
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SSD_Single(0x3D,0x04); //CLK4 -> CLK0
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197
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SSD_Single(0x3E,0x04);
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198
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SSD_Single(0x3F,0x06); //CLK2 -> CLK2
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199
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SSD_Single(0x40,0x06);
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200
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SSD_Single(0x41,0x1F); //VGL
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201
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202
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//GIP_R_GS Pin mapping
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203
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SSD_Single(0x42,0x02); //STV1 -> STV2
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204
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SSD_Single(0x43,0x02);
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205
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SSD_Single(0x44,0x00); //STV2 -> STV0
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206
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SSD_Single(0x45,0x00);
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207
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SSD_Single(0x46,0x1F); //VDS -> VGL
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208
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SSD_Single(0x47,0x1F);
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209
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SSD_Single(0x48,0x1E); //VSD -> VGH
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210
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SSD_Single(0x49,0x1E);
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211
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SSD_Single(0x4A,0x1F); //
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212
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SSD_Single(0x4B,0x17); //VDD2 -> FLM
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213
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SSD_Single(0x4C,0x17);
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214
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SSD_Single(0x4D,0x37); //VDD1 -> INV_FLM
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215
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SSD_Single(0x4E,0x37);
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216
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SSD_Single(0x4F,0x09); //CLK7 -> CLK5
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217
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SSD_Single(0x50,0x09);
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218
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SSD_Single(0x51,0x0B); //CLK5 -> CLK7
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219
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SSD_Single(0x52,0x0B);
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220
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SSD_Single(0x53,0x05); //CLK3 -> CLK1
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221
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SSD_Single(0x54,0x05);
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222
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SSD_Single(0x55,0x07); //CLK1 -> CLK3
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223
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SSD_Single(0x56,0x07);
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224
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SSD_Single(0x57,0x1F); //VGL
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225
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226
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//GIP Timing
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227
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SSD_Single(0x58,0x40);
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228
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SSD_Single(0x5B,0x30); //STV_NUM,STV_S0
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229
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SSD_Single(0x5C,0x16); //STV_S0
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230
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SSD_Single(0x5D,0x34); //STV_W / S1
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231
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SSD_Single(0x5E,0x05); //STV_S2
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232
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SSD_Single(0x5F,0x02); //STV_S3
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233
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SSD_Single(0x63,0x00); //SETV_ON
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234
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SSD_Single(0x64,0x6A); //SETV_OFF
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235
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SSD_Single(0x67,0x73);
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236
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SSD_Single(0x68,0x1D);//CKV_S0
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237
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SSD_Single(0x69,0x08);
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238
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SSD_Single(0x6A,0x6A);
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239
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SSD_Single(0x6B,0x08); //Dummy clk
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240
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241
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SSD_Single(0x6C,0x00);
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242
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SSD_Single(0x6D,0x00);
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243
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SSD_Single(0x6E,0x00);
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244
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SSD_Single(0x6F,0x88);
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245
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246
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SSD_Single(0x75,0xFF);
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247
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SSD_Single(0x77,0xDD);//VEN_EN=1
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248
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SSD_Single(0x78,0x3F);
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249
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SSD_Single(0x79,0x15); //0x0C
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250
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SSD_Single(0x7A,0x17);//VEN_S0
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251
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SSD_Single(0x7D,0x14);//VEN_ON
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252
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SSD_Single(0x7E,0x82); //VEN_OFF
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253
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254
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255
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//Page4
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256
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SSD_Single(0xE0,0x04);
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257
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SSD_Single(0x00,0x0E);
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258
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SSD_Single(0x02,0xB3);
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259
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SSD_Single(0x09,0x61);
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260
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SSD_Single(0x0E,0x48);
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261
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262
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//Page0
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263
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SSD_Single(0xE0,0x00);
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264
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265
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SSD_Single(0xE6,0x02);
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266
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SSD_Single(0xE7,0x0C);
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267
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|
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268
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|
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269
|
//SLP OUT
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270
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|
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271
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SSD_CMD(0x11); // SLPOUT
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272
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Delayms(120);
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273
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|
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274
|
//DISP ON
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275
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|
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276
|
SSD_CMD(0x29); // DSPON
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277
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Delayms(5);
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278
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|
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279
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//--- TE----//
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280
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SSD_Single(0x35,0x00);
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281
|
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